| 摘要 |
PURPOSE:To make a test easier by making operation changeable in a specific mode, such as test mode, etc., and to prevent malfunctions by making the operations unchangeable in an normal mode by providing an inhibit circuit. CONSTITUTION:In a test mode, etc., a CPU 1 outputs the address data of a register 6 to an address bus 2 and, at the same time, data stored in the register 6 to a data bus 3. An address decoder 5 decodes an address and outputs an access signal 8. Since a mode switching signal 4 is set to '1', the access signal 8 appears in the output of an AND gate 10 and the data are written in the register 6. In addition, the state of a control signal 9 changes and the operations of a functional circuit 7 are also changed. Since the signal 4 is set to '0' in a normal mode, the output of the gate 10 becomes always '0' and the data on the data bus 3 are not written in the register 6. Therefore, the state of the signal 9 does not change and the operation of the circuit 7 is also not changed. |
