| 摘要 |
A switched capacitor circuit with a very large time constant. Numerous low frequency analog applications, modems for example, require this type of circuit. The capacitances required to obtain a sufficiently large time constant are reduced over prior art techniques by as much as 50%. The circuit isinsensitive to parasitic capacitances. The circuit comprises a switched input sampling capacitor, an operational amplifier and a first feedback capacitor connected in parallel with the amplifier. The switched sampling capacitor samples an input signal in a first clock phase. A second feedback capacitor is switched during the first phase to sample the output of the operational amplifier; and, in a second phase, it is switched in parallel with the first feedback capacitor of the amplifier. |
