Memory controller for using reserved DRAM addresses for EMS

摘要

A memory controller which can map EMS addresses into the DRAM behind video RAM addresses or other reserved areas of memory. A single chip has both a DRAM decoder and an EMS decoder operating in parallel. A DRAM decoder examines received addresses and provides an enable signal to a DRAM timing circuit if the address is within the DRAM range and not for a reserved group of addresses. A separate EMS decoder provides a translated address when a received address is within an EMS window. The EMS decoder also provides an EMS timing signal to the DRAM timing circuit.