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发明名称
METHOD AND APPARATUS FOR TESTING LOGICAL CIRCUIT
摘要
申请公布号
JPH04310880(A)
申请公布日期
1992.11.02
申请号
JP19910076256
申请日期
1991.04.09
申请人
FUJITSU LTD
发明人
KUDOU TAKEHIRO
分类号
G01R31/3183;G01R31/28
主分类号
G01R31/3183
代理机构
代理人
主权项
地址
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