| 摘要 |
An output buffer circuit is disclosed that has optimized ground bounce characteristics while maintaining low propagation delay. The output buffer may be incorporated within an integrated circuit and may be embodied in either inverting or non-inverting and in either enabling and non-enabling configurations. The output buffer circuit includes a feedback means coupled to the output terminal of the output buffer and to a pull-down transistor. The feedback means provides a feedback voltage to the gate of the pull-down transistor to regulate the derivative of source current with respect to time. The feedback means includes a pair of field effect transistors and either an inverter gate or a NOR gate coupled across one of the feedback field effect transistors. |
