MAPPABLE TEST STRUCTURE FOR GATE ARRAY CIRCUIT AND METHOD FOR TESTING THE SAME

摘要

A set of interconnections is used for testing components (104) of a gate array integrated circuit (100). The gate array integrated circuit has an array (102) of the components (104) arranged in rows and columns and a set of input/output pads (120) along the periphery of the array. The set of interconnections includes component selection interconnections (METAL 1), coupled to all components in a core region (140) of the gate array integrated circuit. These component selection interconnections enable selective activation of predefined groups of the components (104) in the core region. Bit line interconnections (METAL 2) carry test signals generated by activated components in the core region. A separate test signal is generated by each of the components in the core region (140), thereby enabling each of the components in the core region to be individually tested.