| 摘要 |
<p>A single transistor electrically programmable and erasable memory cell (10) is disclosed. The single transistor has a source (14), a drain (16) with a channel region (18) therebetween, defined on a substrate. A first insulating layer (20) is over the source, channel and drain regions. A floating gate (22) is positioned on top of the first insulating layer over a portion of the channel region and over a portion of the source region. A second insulating layer (25) has a top wall which is over the floating gate, and a sidewall which is adjacent thereto. A control gate has a first portion (24) which is over the first insulating layer and immediately adjacent to the sidewall of the second insulating layer. The control gate has a second portion (26) which is over the top wall of the second insulating layer and is over the floating gate. Erasure of the cell is accomplished by the mechanism of Fowler-Nordheim tunneling from the floating gate through the second insulating layer to the control gate.</p> |
