| 摘要 |
PURPOSE:To prevent production of defect of timing without management of clock delay among clock trees. CONSTITUTION:The distributer is provided with plural clock drivers 3,3a-3d, 4a-4d in a clock tree connection distributing a clock signal to synchronizing circuits 5a-5c and a logic gate circuit 6 ORs or ANDs output signals of the clock drivers 2,3a-3d, 4a-4d and an output of the arithmetic operation is inputted to the synchronizing circuits 5a-5c. |
