| 摘要 |
A semiconductor memory device comprises regular memory cells (MC11 to MCmn) arranged in rows and columns, word lines (WL1 to WLm) respectively coupled to the rows of the regular memory cells, a row address decoding circuit (12b) responsive to external address bits for designating one of the word lines, word line driving circuits (131 to 13m) associated with the word lines and driving one of the word lines under the control of the row address decoding circuit, and a row of redundant memory cells (RC1 to RCn) with which one of the rows of the regular memory cells is replaced upon discovering a defective memory cell incorporated therein, wherein breakable elements (F11 to F1m) are coupled between the row address decoding circuit and the word line driving circuits and one of the breakable elements associated with one of the row with the defective memory cell is broken so that any data bit is never read out from the defective memory cell even if the external address bits designate the defective memory cell. <IMAGE> |
