| 摘要 |
A prewrite compensation circuit for selectively delaying the writing of non-zero bits of data streams to disks of a hard disk drive. The hard disk drive includes a write circuit for writing the non-zero bits to selected portions of selected disk surfaces and selected write delays are effected by a variable delay circuit that receives the data stream from a shift register through which the data stream is passed. The amount of delay is determined by a delay word entered into a latch connected between the variable delay circuit and a RAM in which delay words are stored at addresses selected for each delay word in relation to the pattern of bits of the data stream surrounding each non-zero bit, the disk surface to which each data stream is to be written and the portion of the surface to receive the data stream. Encoders connected to the shift register provide a portion of the RAM address to a data latch connected to address terminals of the RAM and a control microprocessor provides stored remainders of the RAM address, corresponding to the disk surface and disk surface portion to which the data stream is to be written, to other address terminals of the RAM.
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