发明名称 |
Apparatus and method for detecting out-of-lock condition in a phase lock loop |
摘要 |
A circuit is provided for detecting out-of-lock condition in a phase lock loop. The phase lock loop receives a first signal having a first frequency and a voltage controlled oscillator of the phase lock loop produces a second signal having a second frequency. The circuit comprises a first data flip-flop coupled to the phase lock loop for receiving the first signal and clocked by the second signal. The first flip-flop produces an inverted output of the first signal. A second flip-flop is coupled to the phase lock loop for receiving the second signal clocked by the first signal, and produces a non-inverted output of the second signal. Additionally, an EXCLUSIVE-OR gate is coupled to the first and second flip-flops for receiving the inverted and non-inverted output thereof and producing a signal indicative of an out-of-lock condition.
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申请公布号 |
US5159279(A) |
申请公布日期 |
1992.10.27 |
申请号 |
US19900618675 |
申请日期 |
1990.11.27 |
申请人 |
DSC COMMUNICATIONS CORPORATION |
发明人 |
SHENOI, KISHAN;WETLE, DAVID J. |
分类号 |
H03K5/26;H03L7/095 |
主分类号 |
H03K5/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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