发明名称 State machine architecture providing increased resolution of output timing
摘要 A circuit allows for improved flexibility in the timing of device output, for example, from a state machine. Output for the device is placed in a first register. The output is forwarded from the first register to a second register. The first register and the second register are clocked on different edges of a clock signal. A selector selects contents of the first register or contents of the second register as the device output for an external device. The selector may be controlled by the contents of one or more flip-flops. When the device is a state machine, the output of each flip-flop may also be used as feedback to the state machine.
申请公布号 US5159278(A) 申请公布日期 1992.10.27
申请号 US19910679379 申请日期 1991.04.02
申请人 VLSI TECHNOLOGY, INC. 发明人 MATTISON, PHILLIP E.
分类号 G06F7/00 主分类号 G06F7/00
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