| 摘要 |
PURPOSE:To obtain the data sampling clock phase locked loop circuit which is inexpensive and small in size and can expect stable operations for a long period since digitization is facilitated. CONSTITUTION:The above circuit is provided with an oscillator 11 to generate the pulse signal of the same frequency as that of a data sampling clock signal which is set on the side of a data transmitter and has an already known frequency, an (n-1) number of delay elements 121-12n-1 to successively delay the phase of the output signal from the oscillator 11 for every 1/n cycle, an (n) number of data latches 131-13n to respectively latch the output signals of the delay elements 121-12n-1 according to data signals transmitted from the data transmitter, a decoder 14 to decoder output signal L1-Ln of the data latches 131-13n, and a selector 15 to select one of the (n) number of signals f1-fn composed of the output signal f1 of the oscillator 11 and the output singnals f2-fn of the delay elements 121-12n-1 as a data sampling clock signal while responding to the output of the decoder 14. |
