COMPATIBLE PROTOCOL FOR MULTIPROCESSOR USING COMMON MEMORY

摘要

PURPOSE: To employ a compatible protocol for the memory sharing multiple processors which have a packet switching type bus together with write-back caches for connecting the individual processors to the bus. CONSTITUTION: This protocol makes it possible to store the caches 16aa-16ij with multiple copies of read/write data in the same physical addresses for use complying with requests of the processors 12aa-12ij. This protocol makes hardware maintain the compatibility of data automatically and transparently. Consequently, when the caches 16aa-16ij have data shared is detected by monitoring the traffic on the bus, and consequently update writing is broadcasted onto the bus each time each of the processors 12aa-12ij writes to a common address. This protocol maintain the compatibility of memories for the processors while allowing I/O devices to gain direct access to the memories.