发明名称 |
MASK LAYOUT METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT |
摘要 |
PURPOSE:To efficiently design a new mask layout on the basis of a mask layout designed in the past by a manual operation. CONSTITUTION:Standard cell information (c) is extracted from an old graphic pattern (f) designed in the past by a manual operation. A netlist (b) is formed from the old graphic pattern (f) by utilizing an existing netlist verification device 30. The netlist (b) which has been format-converted and the standard cell information (c) are given to an existing automatic arrangement and interconnection device 20; in addition, a new design rule (d) is set. When the new design rule (d) is applied to the old graphic pattern (f), a new graphic pattern (g) can be obtained. |
申请公布号 |
JPH04299843(A) |
申请公布日期 |
1992.10.23 |
申请号 |
JP19910089568 |
申请日期 |
1991.03.28 |
申请人 |
DAINIPPON PRINTING CO LTD |
发明人 |
NISHIMURA HISATOSHI;NAKAZAWA ATSUSHI |
分类号 |
G03F1/68;G03F1/70;G06F17/50;H01L21/027;H01L21/30;H01L21/82;H01L21/822;H01L27/04 |
主分类号 |
G03F1/68 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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