| 摘要 |
The present invention relates to an integrated test circuit for a matrix array in which each memory point or image point (1), defined at the intersection of two arrays of orthogonal conductors consisting of N rows (L1 to LN) and M columns (C1 to CM), includes at least one switching element, the rows and columns being connected respectively to at least one addressing circuit and one control circuit. This circuit consists of at least two additional columns (C1D, C2D) and two additional rows (L1B, L2B) produced on the side away from the addressing circuit and the control circuit, the two columns and the two rows being connected together at the level of each row and each column by a switching circuit (4) controlled by a pulse applied to at least the said row and at least the said column. Application to liquid crystal screens and RAM memories. <IMAGE>
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