| 摘要 |
The system is for writing/reading one frame data into/from DRAMs without extra refresh controller to simplify the concerned circuits and reduce the cost of manufacturing. The system includes a TBC (20) for supplying time-axis corrected digital video signal to an adder (40) and a data selector (34), 1st and 2nd frame memories (31,32) for storing the digital video signal from the TBC (20) and sending it to the adder (40), data selector (34) for writing/ reading data into/from the 1st and 2nd frmae memories (31,32), and a timing block (33) for accessing the address in the memories. |
