发明名称 CLOCK REPRODUCING CIRCUIT
摘要 <p>PURPOSE:To control the frequency of a read clock in accordance with the frequency of a write clock for the purpose of setting the picture data storage capacity of a FIFO memory to a proper value. CONSTITUTION:A correction value corresponding to the picture data storage capacity of a FIFO memory 22 is outputted from a correction value generating circuit 23. This correction value is added to a transmission-side sampling clock (which may be equal to the write clock) by an adder 24 to obtain a corrected sampling clock. A reproduced sampling clock is outputted from a voltage controlled oscillator 16 as the read clock based on the corrected sampling clock and a transmission line clock.</p>
申请公布号 JPH04299653(A) 申请公布日期 1992.10.22
申请号 JP19910085903 申请日期 1991.03.27
申请人 NEC CORP;NEC MIYAGI LTD 发明人 YAMADA HIROKI;SHIBUYA TORU
分类号 H04N1/21;H04J3/06;H04N1/00;H04N1/41;H04N7/56 主分类号 H04N1/21
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