| 摘要 |
<p>PURPOSE:To reduce the number of parts by providing an address comparator circuit for judging that the row addresses of following bus cycles are coincident. CONSTITUTION:An address comparator circuit 14 is provided in addition to a prefetch unit 11, instruction decoder 12, execution unit 13, data bus interface 15, address bus interface 16, inside data bus 17 and inside address bus 18. This address comparator circuit 18 compares the row address of a memory designated by the bus cycle under execution at present with the row address of a memory designated by the preceding bus cycle and judges whether those row addresses are coincident or not. Namely, the address of the random access memory designated by the first bus cycle under execution at present is compared with the address designated by the second bus cycle as the bus cycle preceding to the first bus cycle, and the compared result is outputted.</p> |
