| 摘要 |
The circuit performs interpolation of a video signal (G) from a CCD device to improve the image quality of the video signal. The circuit comprises a first pitch delay unit (10) for sampling a sampled and held video signal to output a first delay signal (I), a decimation unit (20) for sampling the separated video pulse trains (L,M) to output the sampled video pulse trains (J,K), a second pitch delay unit (30) for sampling the odd train of video signal (L) sampled and held to output a second delay signal (N), a third pitch delay unit (40) for sampling the even train of video signal (M) sampled and held to output a third delay signal (O), two arithmetic units (50,60) each connected to the outputs of the units (30,40) and an adder (70) for receiving the interpolated video pulses to output a quality-improved video signal.
|
