| 摘要 |
PURPOSE:To securely prevent synchronizing step-out and to improve line quality by ensuring handling of a grid due to clock's fluctuation when inputted radio waves are weak. CONSTITUTION:The above receiver is provided with a pulse generation circuit 10 which generates a short pulse wider than the grid and synchronizes with the starting-up of the clock on the side with stronger waves, a delay circuit 11 which delays the clock on the side with stronger waves by the starting-up time of the short pulse, an AND gate 12 which outputs the logical product of the clocks from the pulse generation circuit 10 and the delay circuit 11 as a demodulation clock, and a PLL circuit 20 which stablizes a frequency concerning the demodulation clock from the AND gate 12. |
