发明名称 |
DRAM HAVING EXTENDED REFRESH TIME |
摘要 |
A DRAM is described including a plurality of operable storage cells, each cell including a capacitance for storing a charge indicative of data. The charge tends to dissipate below an acceptable level after a predetermined time interval T1 for a majority of the operable cells and for a minority of the operable cells, it dissipates below the acceptable level after a shorter time interval T2. The time between DRAM refresh cycles is adjusted so as to be greater than time interval T2. The DRAM comprises: a plurality of redundant storage cells; a decoder for receiving the address of an operable memory cell and providing a first output if the address indicates one of the operable cells of the minority of cells and a second output if the address indicates one of the operable cells of the majority. A switching circuit is responsive to the first output to enable access of a redundant stoarge cell and to prevent access of the minority storage cell. In a preferred embodiment, the redundant storage cells are configured as static storage circuits.
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申请公布号 |
US5157634(A) |
申请公布日期 |
1992.10.20 |
申请号 |
US19900602037 |
申请日期 |
1990.10.23 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
DHONG, SANG H.;FRANCH, ROBERT L.;HWANG, WEI |
分类号 |
G11C11/401;G11C11/406;G11C29/00;G11C29/04 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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