发明名称 |
VARIABLE DECIMATION ARCHITECTURE FOR A DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTER |
摘要 |
An analog-to-digital converter includes a delta-sigma modulator (10), having the output thereof filtered by a digital filter section. The digital filter section includes a first fixed decimation filter (12) followed by a variable decimation filter section (14) and an output low-pass filter section (16), having a fixed decimation ratio. The fixed variable decimation filter section (14) includes a single FIR filter (24) that has data processed therethrough with different sampling rates. A recursive controller (26) receives an external configuration input to determine the number of passes through the filter (24) that are required to provide the desired decimation ratio.
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申请公布号 |
US5157395(A) |
申请公布日期 |
1992.10.20 |
申请号 |
US19910664034 |
申请日期 |
1991.03.04 |
申请人 |
CRYSTAL SEMICONDUCTOR CORPORATION |
发明人 |
DEL SIGNORE, BRUCE;SWANSON, ERIC J.;KLAAS, JEFFREY M.;MEDLOCK, DAVID L. |
分类号 |
H03H17/02;H03H17/06 |
主分类号 |
H03H17/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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