| 摘要 |
PURPOSE: To provide an adjustable delay device adopted to a digital data transmission system having an extremely high rate. CONSTITUTION: The adjustable delay device 10 includes the load resistances 14 and 15 of transistors 12 and 13, and an ECL gate 11 combined with an adjustment circuit 23 for operating to the resistance value of the load resistance 18 of the source 16 of the ECL gate 11 in order to change a current generated from the source 16 into a line shape while maintaining a voltage on the collectors of the transistors 12 and 13 constant. The range of the change of the resistance is selected so that delays between input signals IN, IN' and OUT, OUT change almost linearly. |
