发明名称 TROUBLE SIMULATION METHOD FOR SEMICONDUCTOR DEVICE AND DATA PREPARATION DEVICE FOR TROUBLE SIMULATION
摘要 <p>PURPOSE:To shorten the simulation processing time for the trouble simulation method for a semiconductor device and a data producing device for the trouble simulation. CONSTITUTION:A function block terminal detecting part 6 detects each of input and output terminals of each function block consisting of plural basic gates. A net data detecting part 7 detects the net data on each detected input or output terminal of each function block. A basic gate terminal detecting part 8 detects the input or output terminal of the gate corresponding to each detected net data. An assumptive trouble eliminating part 9 eliminates the troubles except those assumptive once of the gate input or output terminal detected by the part 8 among all assumptive troubles defined at the input or output terminal of each basic gate of a corresponding function block. Then the part 9 prepares the data on a trouble eliminating circuit.</p>
申请公布号 JPH04291459(A) 申请公布日期 1992.10.15
申请号 JP19910055225 申请日期 1991.03.20
申请人 FUJITSU LTD;FUJITSU VLSI LTD 发明人 NISHIKAWA NAOTO
分类号 G01R31/28;G06F17/50;G06F19/00 主分类号 G01R31/28
代理机构 代理人
主权项
地址