| 摘要 |
The system is for asynchronous serial communication by using hardware that latches and buffers the data to be a pplicable to Tx/Rx communication and software that sets data format suitable for asynchronous communication. The system includes a digital signal processor (5), a Rx/Tx buffer (2) for buffering the receiving/ transmitting data, and a flipflop (4) for sending data reception start signal to the digital signal processor (5) through a D-flipflop (F/F1).
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