摘要 |
A central processor for scientific-technical, economic-statistical calculations, simulation and control usage, provided with a wide command word architecture comprises buffer memories (1) and (3) of commands and words, a controlling device (2), a data commutator (4), an arithmetic-logic unit (5), units (6-11) for data record calling, indexation, associative storage, conversion of a mathematical address into a physical one, interfacing and subprogramming, as well as a control sentinel unit (13) and an operand availability unit (14), and characterized by high performance in both vector and scalar computations. |
申请人 |
INSTITUT TOCHNOI MEKHANIKI I VYCHISLITELNOI TEKHNI |
发明人 |
BABAIAN, BORIS ARTASHESOVICH;VOLKONSKY, VLADIMIR JURIEVICH;GORSHTEIN, VALERY YAKOVLEVICH;KIM, ALEXANDR KIIROVICH;NAZAROV, LEONID NIKOLAEVICH;SAKHIN, JULY KHANANOVICH;SEMENIKHIN, SERGEI VLADIMIROVICH |