发明名称 TEST VECTOR GENERATOR FOR LOGICAL IC TESTER
摘要 PURPOSE:To economize an apparatus by reducing the capacity of a scanning vector memory storing the scanning control data and scanning data supplied to an IC to be tested. CONSTITUTION:A scanning vector memory 21 has N1 channels corresponding to N1 scanning control terminals of an IC to be tested and N2 channels common to respective circuits respectively having N2 scanning data terminals and successively stores the scanning data during the test period of the respective circuits. During the test period, the outputs of the respective channels of the memory 21 are inputted to a muliplexer 36 and selected so as to be changed over by a multiplexer control memory 51 to be outputted to N output terminals P1-PN of an apparatus. In this apparatus, the capacity of the memory 51 or a control data memory 30 is increased but the increase quantity thereof is far small as compared with the reducible capacity of the memory 21. Therefore, large economization can be achieved.
申请公布号 JPH04289472(A) 申请公布日期 1992.10.14
申请号 JP19910052756 申请日期 1991.03.18
申请人 ADVANTEST CORP 发明人 ICHIYOSHI SEIJI
分类号 G01R31/3183;G01R31/28;G06F11/22 主分类号 G01R31/3183
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