发明名称 PHASELOCKED LOOP CIRCUIT
摘要 PURPOSE:To prevent a jump of a frequency of a VCO at the restoration of an input clock by using a N/2 frequency division pulse of the VCO so as to keep an output of a coupling circuit to a required control voltage level at the clock input interruption. CONSTITUTION:When an input interruption detection circuit 1 detects a clock interrupt, A phase comparator circuit 4 segmenting a signal with a pulse of 1/N frequency division via a 1/N frequency divider circuit 2 segments an output of a VCO 9 by using a pulse of N/2 frequency division by a N/2 frequency divider circuit 10. On the other hand, a phase comparator 5 inhibits the set of an FF 21 at the interruption and uses the N/2 frequency division pulse of the VCO 9 to repeat the inversion of a FF 21. Thus, a duty of an input pulse to a coupling circuit 8 is close to 50% and an output level of the circuit 8 reaches a level at which the VCO 9 outputs a center frequency and jump of an output frequency is prevented when the input clock is restored.
申请公布号 JPH04290011(A) 申请公布日期 1992.10.14
申请号 JP19910080808 申请日期 1991.03.18
申请人 NEC CORP 发明人 KADOWAKI MAKOTO
分类号 H03L7/10;H03L7/14 主分类号 H03L7/10
代理机构 代理人
主权项
地址