| 摘要 |
PURPOSE:To increase the read-in margin, by making the level of bit line pair to the read level, through the connection of dummy cell group with dummy bit line pair by the arrangement toward bit line and the connection of the bit line pair to the base of detection transistors. CONSTITUTION:The dummy cell DC group is arranged toward the bit line B at a suitable location lengthwise the word line W, and each of them is connected to the respective word line W and common dummy bit line DB line pair. Further, this bit line DB pair is connected to the base of detection transistors T8, T10 and the voltage level of the bit line DB pair is taken as the read level RL. For example, the circuit as shown in Figure is constituted with the memory cell MC using FF consisting of multiemitter transistors Q1, Q2, dummy cell DC with the same construction, and constant current sources J1-J7 and the like, so that the transistors in o-mark are ON and those in x-mark are OFF. |
