| 摘要 |
PURPOSE:To reduce the time of conversion of an analog-digital converter, by switching the variable current source immediately after the end of the first operation of a comparator. CONSTITUTION:When the sample-held input analog voltage is applied to the input terminal 1, the register 6 is reset by the control of the timing circuit 8. Thus the output of the D/A converter 7 is set to zero, and at the same time the current value of the variable current source 4 is set to 10. Then the latch enable signal is applied to the comparators 2-1-2-7 from the timing circuit 8 to carry out a comparison, and the A/D conversion output of higher 3 bits is stored in the register 6. The current value of the source 4 is switched by the control of the circuit 8 as soon as the above- mendioned comparison ends with the comparators 2-1-2-7. In parallel to this switching action, the output of the register 6 is converted into the analog voltage through the converter 7 to be used as a new standard voltage. After this, the A/D conversion of the lower 3 bits is carried out in the same way. |
