发明名称 PN PATTERN CHECK CIRCUIT
摘要 PURPOSE:To conduct the test with an optional frame spread arrangement pattern to a multi-frame with respect to the PN pattern check circuit used for a time division multiplex bus tester testing the data communication of a time division multiplex bus in the time division multiplex multi-frame communication system by means of loopback information of a PN pattern data. CONSTITUTION:The circuit is provided with frame setting means 11-1n provided corresponding to each multi-frame and allocating a PN pattern data sent/ received in each frame and a parallel/serial conversion means 2 converting a frame setting parallel signal outputted from the frame setting means 11-1n into a serial signal.
申请公布号 JPH04287530(A) 申请公布日期 1992.10.13
申请号 JP19910052519 申请日期 1991.03.18
申请人 FUJITSU LTD 发明人 YOTSUMARU TAKEO
分类号 H04J13/00 主分类号 H04J13/00
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