发明名称 DIVIDER CIRCUIT
摘要 The division circuit has fast processing time by utilizing neural network. The division circuit includes an input synapsis group (11) for coupling a first power (Vcc) and output lines with strength of input bits, a first bias synapsis group (12) for coupling a first power (Vcc) and output lines with unit coupling strength, a second bias synapsis group (13) for couplling output lines and a second input power (GND) with strength of added value of output bits, a feedback synapsis group (14) for coupling a second power (GND) and lower bit output lines with strength of added value of upper output bits, a neuron group (15) for sending excited or ground state according to coupling state of the first power and the second power, and inverter group (16) for inverting output bits of the neuron group (15).
申请公布号 KR920009092(B1) 申请公布日期 1992.10.13
申请号 KR19900004515 申请日期 1990.04.03
申请人 JONG, HO - SON 发明人 JONG, HO - SON;KIM, SHIN - JIN;KIM, TAE - HUN
分类号 G06F7/52;G06F7/535;G06N3/063;(IPC1-7):G06F7/52;G06F15/18 主分类号 G06F7/52
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