| 摘要 |
PURPOSE:To realize the clock recovery system contributing to high reliability of a LAN by providing flexibility not effected even when plural reference clock sources of plural data lines accommodated in the LAN are in use and operating lines other than a faulty line without hindrance even when an external reference clock is tentatively interrupted by a master node with respect to the LAN in which a prescribed quantity of data sent to the transmission line is received by a slave node and outputted to a terminal equipment by using a master clock generated in its own PLL of the master node with a reference clock. CONSTITUTION:Each slave node 21 is provided with a PLL circuit 1 reproducing and outputting a clock CK in subordinate synchronization with a master clock MCLK of an output of a master node 10, a reception buffer FIFO 2 storing a prescribed multi-value processing of a reception data DR resulting from a transmission data DT to a transmission line from the master node by using the output CK of the PLL circuit and a monitor circuit 3 monitoring the data storage quantity of the reception buffer, and the monitor circuit 3 monitors the data storage quantity of the reception buffer 2 to regulate the speed of the output clock CK of the PLL circuit 1 thereby allowing the slave node 21 to receive a prescribed quantity of data sent from the master node 10 to the transmission line synchronizingly. |
