发明名称 POWER ON RESET DEVICE
摘要 <p>PURPOSE:To supply a power on reset device which can generate a stable pulse by correcting the variance of thresholds owing to manufacture processes. CONSTITUTION:The respective sources of two P-channel transistors are connected to a power source. The gate of the first P-channel transistor P1 is connected with ground and its drain is connected to ground by way of a node 1 and a capacitance C1. The source of the second P-channel transistor P2 is connected with the node 1 and its drain is connected with ground as output by way of a resistance R1.</p>
申请公布号 JPH04286012(A) 申请公布日期 1992.10.12
申请号 JP19910051020 申请日期 1991.03.15
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YAJIMA SHINJI
分类号 G06F1/24 主分类号 G06F1/24
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