| 摘要 |
PURPOSE:To reduce the circuit scale of the deflection device comprising a vertical synchronizing signal processing circuit and a deflection correction waveform generating circuit. CONSTITUTION:A count (X) resulting from counting a timing signal whose frequency is twice (2fH) the horizontal frequency counted by a vertical synchronizing signal processing circuit 100 is fed to a register 300 via a bus line 6 and the count (X) is fed to a RAM 24 of a deflection correction waveform generating circuit 200 from the register 300 via a bus line 26. |
