| 摘要 |
PCT No. PCT/SE93/00065 Sec. 371 Date Sep. 19, 1994 Sec. 102(e) Date Sep. 19, 1994 PCT Filed Jan. 29, 1993 PCT Pub. No. WO93/15556 PCT Pub. Date Aug. 5, 1993An analog-to-digital arrangement for A/D converting a high-frequency analog input signal into a series of digital signals on-line with high sampling rate. It includes several computing channels for providing a digital signal from an analog input, each including a sample-and-hold means, to which the analog input signal is connected, a multiplexing means having several inputs, each input being connected to an individual computing channel output, and, a timing circuit controlling cyclically in a clock signal rate and in a prescribed order one at the time of the sample-and-hold means to hold the current analog value of the analog input signal and also to control the multiplexing means to place on its output one at the time of the digital outputs of the several computing channels. All the computing channels compute the digital value of the analog value held in its sample-and-hold means during a digitizing phase simultaneously but skewed in relation to the other computing channels. |
