| 摘要 |
PURPOSE:To efficiently detect and correct a fault by providing an ECC circuit which can correct 1-bit faults and detect 2-bit faults, parity inspection circuit, and bits exclusively used for reporting faults. CONSTITUTION:A control storage control circuit is provided with a parity inspection circuit 5 and ECC circuit 6 and a memory 2 is provided with bits 10 and 11 exclusively used for reporting faults. The circuit 5 is used for detecting 1-bit faults and the circuit 6 is only used for detecting 2-bit faults and correcting 1-bit faults. In addition, since fault reporting is made by using the circuit 5 and bits 10 and 11, fault reports can be performed at a high speed, execution of a microinstruction by means of data read out from a memory containing a fault can be frozen at a high speed, and the freezing of the execution can be canceled after the circuit 6 corrects the data read out from a faulty address by reloading. Therefore, the rate of success of the reexecution of a microinstruction is improved and the malfunction of the microinstruction is minimized. |
