| 摘要 |
PURPOSE:To obtain a stable synchronization clock with phase locking to an input burst data even at burst halt. CONSTITUTION:Since a tank circuit 2 cannot extract a clock component at burst halt, no extraction clock signal (e) is obtained. In this case, a selector 6 uses a burst phase control signal (b) to select an internal clock signal (f) as a selection clock signal (g). A phase comparator 3 implements phase comparison by using the selection clock signal (g) as a reference input and the internal clock signal (f) as a comparison input to output a voltage signal (c) in response to a phase difference. In this case, the phase comparator 3 compares the internal clock signals (f). Thus, the phase synchronization at burst reception is completely held. |
