| 摘要 |
A calibrated digital-to-analog converter (DAC) is provided that includes a DAC having an interpolation circuit (40) and delta-sigma converter (44). The output of the delta-sigma converter (44) is input to a one-bit DAC (48) and the output thereof filtered by an analog low pass filter section (50). During a calibration procedure, a calibrated analog-to-digital converter (ADC) (22) is utilized that is operable to receive the analog output of the DAC with a "0" value input thereto through a multiplexer (58). The output of the ADC (22) represents the inherent error in the delta-sigma converter (44) and the analog filter section (50). This is stored in a register (62). In a second step of the operation, the contents of the register (62) are input through the interpolation circuit for interpolation thereof and storage in an offset register/latch circuit (56). The contents of the latch (56) are input to a summing junction (54) which, in normal operation, are summed with the output of the interpolation circuit (40) for input to the delta-sigma converter (44). By disposing the summing junction (54) between the interpolation circuit (40) and the delta-sigma modulator (44), the bit load on the input of the interpolation (40) can be reduced. By utilizing the interpolation circuit (40) in the calibration procedure, the gain thereof can be compensated for in the value stored in the register/latch (56).
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