发明名称 Logic circuit using element having negative differential conductance
摘要 A logic circuit includes n input terminals where n is an odd integer, an output terminal, and n input resistance elements respectively connected to the n input terminals. The logic circuit also includes a negative differential conductance element having a negative differential conductance in which the negative differential conductance element outputs a peak voltage and a valley voltage higher than the peak voltage. The negative differential conductance element has a first terminal coupled to the n input terminals via the n input resistance elements, and a second terminal. The negative differential conductance element outputs a first group of voltages lower than the peak voltage to the second terminal when the number of input terminals which are at a low level is greater than the number of input terminals which are at a high level, and outputs a second group of voltages to the second terminal when the number of input terminals which are at the high level is greater than the number of input terminals which are at the low level. Further, the logic circuit includes an output circuit which outputs a first voltage indicating the first group of voltages to the output terminal and which outputs a second voltage indicating the second group of voltages.
申请公布号 US5153461(A) 申请公布日期 1992.10.06
申请号 US19900620033 申请日期 1990.11.30
申请人 FUJITSU LTD. 发明人 TAKATSU, MOTOMU
分类号 H03K3/36;H03K19/08;H03K19/23 主分类号 H03K3/36
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