| 摘要 |
PURPOSE: To provide a manufacturing method of a self-aligned complementary heterostructure FET which is fast and small in power consumption. CONSTITUTION: On a semi-insulating substrate 12, a low-band-gap III-V-group semiconductor layer 18 is formed. After a 1st insulator layer 20 is formed on it, a 1st opening part 22 and a 2nd opening part 24 are formed penetrating the 1st insulator layer 20 and a III-V-group layer 18. After insulator spacers 26 are formed of 2nd insulating materials on the side walls of the 1st and 2nd opening parts, gates 28 and 30 are formed in the respective opening parts. The 1st insulator layer 20 is substantially removed and a source-drain area is formed in an area close to the III-V layer and the gate in the substrate so as to self- align with the gate. After an isolation area is formed between elements, formation is performed by using a material having the same ohmic contact with the source-drain area so that self-aligning with the gate is made.
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