Biasing network for use with field effect transistor ring mixer

摘要

A biasing network for use in conjunction with a mixer employing field effect transistors which provides for minimum conversion loss over a range of process and temperature conditions. The biasing circuit includes a first field effect transistor having a small gate periphery which is configured as a current source, a second or reference field effect transistor having a gate periphery substantially equal to the gate peripheries of the transistors in the mixer to which the biasing circuit is providing DC biasing voltages and a voltage divider which is functional in defining operating conditions for the reference transistor.