发明名称 CLOCK CONTROL CIRCUIT
摘要 <p>PURPOSE:To lover the circuit operating rate of an information processor and to reduce power consumption and heating value in a circuit by detecting the operation awaiting state of a functional block, and stopping a clock in the awaiting state. CONSTITUTION:When an operation request acceptance signal 203 for an operation request sending signal 101 is inputted from another block, an awaiting state detection circuit 20 outputs a clock start-up request signal 201, and starts up a second operation by setting a clock control flip-flop 30. Simultaneously. the signal 203 is also inputted to an operation request circuit 10, and the output of the signal 101 is completed. After the lapse of constant time, the awaiting state detection circuit 20 outputs the signal 101, and stops the second operation. In such a way, since an operating clock Is stopped in the operation awaiting state, no circuit processing part is operated ordinarily.</p>
申请公布号 JPH04279912(A) 申请公布日期 1992.10.06
申请号 JP19910003049 申请日期 1991.01.16
申请人 NEC CORP 发明人 UEDA KATSU
分类号 G06F1/04 主分类号 G06F1/04
代理机构 代理人
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