| 摘要 |
A switching network including one or more switching circuits and a control circuit (CCC), the switching circuit including a time division switching element (SR12-SR78) provided with inputs and outputs for data packets and the switching element being controlled by the control circuit (CCC). This switching element is constituted by a closed loop shift register (SR12-SR78) of which all the stages are controlled by a clock signal (f2) provided by the control circuit (CCC) and form a number of shift register portions (SR12-SR78) which are each (SR12) associated to a parallel input (h12) having access to all stages of this portion. A plurality of inputs (R1/2) of the switching element have access to this parallel input (h12) via a multiplexer (MUX12). |
