| 摘要 |
<p>PURPOSE: To provide a bias circuit for reading any selected cell inside a semiconductor memory cell array. CONSTITUTION: A semiconductor memory cell 10 is connected to a drain column line 19, source column line 17 and word line 15. The bias circuit is provided with a common node N, a resistor means T12 connected between this node N and the source and drain column lines 17 and 19, a drain selecting means T15 for transmitting a 1st bias voltage to the selected drain column line during a read cycle, a source selecting means T14 for transmitting a 2nd bias voltage to the source column line, and a reference selecting means T13 for connecting the source column line to a reference potential Vss. A sense amplifier and a driver circuit are respectively provided with three transistors T1-T11 at least and have outputs connected to the drain column line and source column line of a memory array.</p> |
