发明名称 Sample-and-hold circuit.
摘要 <p>A sample-and-hold circuit including two capacitors (13, 17) connected to an input signal line (25) through their respective analog switches (12, 16) for holding an input signal voltage, and an amplifier circuit (190) having two input terminals, (190a, 190b) for receiving voltages held in the two capacitors respectively for amplifying the received voltages. The amplifier circuit alternately amplifies the voltages received through the two input terminals. &lt;IMAGE&gt;</p>
申请公布号 EP0506344(A2) 申请公布日期 1992.09.30
申请号 EP19920302539 申请日期 1992.03.25
申请人 SHARP KABUSHIKI KAISHA 发明人 SANO, YOSHIKI
分类号 G11C27/02 主分类号 G11C27/02
代理机构 代理人
主权项
地址