| 摘要 |
PURPOSE:To decrease the number of entries for storage of degraded bits compared with an address array and to improve the performance of a cache memory with a small hardware quantity by providing a degraded bit for each entry of the address array in order to minimize the delay time caused by the cache fault processing and also providing a degraded bit storage means independently of the address array in order to succeed the cache fault. CONSTITUTION:An information processor includes a data array 30 which stores the copy of the data on a main storage and an address array 20 which stores the address information stored in the main storage and showing the data of the array 30 and the information showing a valid or invalid state as the entries. In such a constitution, a degraded bit is provided in each entry of the array 20 to show a fact that the entry is available together with a degraded bit storage means provided independently of the array 20 for a cache memory. |
