| 摘要 |
A digital signal processing circuit comprising two memory groups to sequentially store digital data of transmission rate t input by a frame unit, a first controller to control the memory groups so that one of the memory groups simultaneously reads out the stored digital data at transmission rate t/n while another memory group sequentially stores the digital data, a signal processor to sequentially signal-process digital data of n systems alternately output from the two memory groups on DAT format, respectively; two other memory groups to alternately store the data signal-processed by the signal processing means, respectively, and a second controller to control the two other memory groups so that one of the two other memory groups outputs the stored and signal-processed digital data at a velocity n times as great as that on memory in a predetermined sequential manner while the other memory groups store the signal-processed data output from the signal processor.
|
