| 摘要 |
A digital noise eliminator whose noise elimination time (noise pulse width or noise frequency) can be determined by the shift time of a shift register activated in response to a reference clock comprises a shift circuit for transmitting an input signal at a second time of the up-edge of the clock as an output signal, only when at least two up-edges of the clock are included in the single input signal, after the input signal has been inputted, and for eliminating noise when only one up-edge of the clock is included in the single input signal; a setting circuit for setting the shift circuit when the input and output signal levels are both at high level; and a reset circuit for resetting the shift circuit when the input and output signal levels are both at low level.
|
